page 1 april 2003 FS8107E low power ph ase-locked loop ic princeton technology corp. reserves the ri ght to change the product described in this datasheet. all information con- tained in this datasheet is subject to change without prior notice. princeton technology corp. assumes no responsibility for the use of any circuits shown in this datasheet. description the FS8107E is a serial data input, phase-loc ked loop ic with prog rammable input and reference frequency dividers . when combined with a vc o, the FS8107E becomes the core of a very low power frequency synthe sizer well-suited for mobile communication applications such as paging systems. compared to the fs8100, the FS8107E is housed in a smaller package and also implements a separate pin for stand-by control. features ? high maximum input operating frequency ? 100 mhz at v dd1 = 1.0 v ? up to 22 mhz internal crystal os cillator reference frequency at v dd1 = 1.0 v ? extremely low current consumption (i dd,total typically 0.4 ma at f fin = 90 mhz) ? 16-bit programmable input fr equency divider (including a 32/33 prescaler) with divide ratio range from 992 to 65535 ? 13-bit programmable reference frequency divider (including a 8 prescaler) with divide ratio range from 40 to 65528 ? optional lock detector output ? charge pump output for passive low-pass filter ? quick-lock signal output for faster locking ? separate pin for stand-by control ? tssop 16l package (0.65mm pitch) applications ? pager ? wireless communication system
FS8107E page 2 april 2003 package and pin assignment: 16l, tssop note: tolerance + 0.1mm unless otherwise specified symbols dimensions in mm dimensions in inch min. nom. max. min. nom. max. a --- --- 1.20 --- --- 0.048 a1 0.05 --- 0.15 0.002 --- 0.006 a2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 --- 0.30 0.007 --- 0.012 c 0.09 --- 0.20 0.004 --- 0.008 d 4.90 5.00 5.10 0.193 0.197 0.201 e --- 6.40 --- --- 0.252 --- e1 4.30 4.40 4.50 0.169 0.173 0.177 e --- 0.65 --- --- 0.026 --- l 0.45 0.60 0.75 0.018 0.024 0.030 y --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8 xin xout vdd2 db do vss fin vdd1 test nc opr le data clk ld nc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 himark FS8107E
FS8107E page 3 april 2003 pin descriptions block diagram number name i/o description 1xin i reference crystal oscillator or external clock input with internally biased amplifier (any external input to xin must be ac-coupled) 2 xout o reference crystal oscill ator or external clock output 3 vdd2 power nominal 3.0 v supply voltage 4 db o single-ended quick-lock ou tput for faster locking 5 do o single-ended charge pump ou tput for passive low pass filter 6 vss gnd ground 7fin i vco frequency input with internally biased input amplifier (any external input to fin must be ac-coupled) 8 vdd1 power nominal 1.0 v supply voltage 9 nc nc no connection 10 ld o lock detector output (high when pll is locked) 11 clk i shift register clock input 12 data i serial data input 13 le i latch enable input 14 opr i battery-save control input; normal oper ation when high, stand-by mode when low 15 nc nc no connection 16 test i test mode control input wi th internal pull-down resistor pfd charge pump fin data clk le test xin control logic n-counter r-counter shift register n-latch r-latch 8 32/33 ld do xout lock detector quick- db window generator opr lock
FS8107E page 4 april 2003 absolute maximum ratings v ss = 0 v recommended oper ating conditions v ss = 0 v parameter symbol rating unit supply voltage v dd1 v ss ? 0.3 to v ss + 2.0 v v dd2 v ss ? 0.3 to v ss + 7.0 v input voltage range v fin v ss ? 0.3 to v dd + 0.3 v operating temperature range t opr ?10 to 60 o c storage temperature range t stg ?40 to 125 o c soldering temperature range t sld 255 o c soldering time range t sld 10 s parameter symbol va l u e unit min. typ. max. supply voltage range v dd1 0.95 1.0 2.0 v v dd2 2.0 3.0 3.3 v operating temperature t a ?10 25 60 o c
FS8107E page 5 april 2003 electrical characteristics (v dd1 = 0.95 to 2.0 v, v dd2 = 2.7 to 3.3 v, v ss = 0 v, t a = 0 to 60 c unless otherwise noted) parameter symbol condition va l u e unit min. typ. max. current consumption i dd,total v dd1 = 1.0 v, opr=?h?, v fin = 0.3 v pk-pk sinusoid, f fin = 100 mhz, v xin = 0.3 v pk-pk sinusoid, f xin = 12.8 mhz 0.40 1.10 ma standby current consumption (i dd2 )i dd,standby v dd1 = 0 v, opr=?l? 10 a fin max. operating frequency f fin,max v fin = 0.3 v pk-pk sinusoid 100 mhz fin min. operating frequency f fin,min v fin = 0.3 v pk-pk sinusoid 40 mhz xin max. operating frequency f xin,max v xin = 0.3 v pk-pk sinusoid 22 mhz xin min. operating frequency f xin,min v xin = 0.3 v pk-pk sinusoid 7 mhz fin input voltage swing v fin 0.3 v pk-pk xin input voltage swing v xin 0.3 v pk-pk clk, data, le logic low input voltage v il 0.3 v clk, data, le logic high input voltage v ih 1.5 v xin logic low input current i il,xin v il = 0 v 10 a xin logic high input current i ih,xin v ih = v dd1 10 a fin logic low input current i il,fin v il = 0 v 60 a fin logic high input current i ih,fin v ih = v dd1 60 a do logic low output current i ol,dop v ol = 0.4 v 1.0 ma do logic high output current i oh,dop v oh = v dd2 ? 0.4 v 1.0 ma ld, fv, fr logic low output current i ol v ol = 0.4 v 0.1 ma ld, fv, fr logic high output current i oh v oh = v dd2 ? 0.4 v 0.1 ma data to clk setup time t su1 2 s clk to le setup time t su2 2 s hold time t hold 2 s
FS8107E page 6 april 2003 functional description programmable input frequency divider the vco input to the fin pin is divided by the programmable divider and then internally output to the phase/frequency detector (pfd) as f v . the programmable input frequency divider consists of a 32/33 ( p / p +1) dual-modulus prescaler and a 16-bit ( n ) counter, which is further comprised of a 5-bit swallow ( a ) counter, and a 11-bit main ( b ) counter. the total divide ratio, m , is related to values for p , a , and b through the relation with the minimum programmable diviso r for continuous counting is given by and the valid total divide ratio range for the input divider is programmable reference frequency divider the crystal oscillator output is divided by the programmable divider and then internally output to the pfd as f r . the programmable refere nce frequency divider consists of a fixed 8 ( s ) prescaler and a 13-bit reference ( r ) counter. the total divide ratio, t , is related to values for s and r through the relation the usable divisor range of reference counter is and therefore, the valid total divide ratio range for the refere nce divider is (in steps of 8.) serial input data format the divide ratios for the input and reference dividers are i nput using a 17-bit serial inter- face consisting of separate clock (clk), data (data), and latch enable (le) lines. the format of the serial data is shown in fig. 1. the data on the data line is written to the shift register on the rising edge of the clk signa l and is input with msb first, and the last (17th) bit is used as the la tch select control bit. the da ta on the data line should be changed on the falling edge of clk, and le s hould be held low while data is being writ- ten to the shift register. data is transferred fr om the shift register to one of the frequency divider latches when le being set high. when the 17th bit is set low, data is loaded to the 16-bit n -counter latch, and when the 17th bit is se t high, the 13 msbs are loaded to the mp 1 + () ap ba ? () + pba , + == ba . pp 1 ? () 32 31 992, == m 992 to 65535. = tsr 8 r . == r 5 to 8191, = t 40 to 6552 8 =
FS8107E page 7 april 2003 13-bit r -counter latch and the remaining 3 lsbs are used to contro l testing modes and should be set as follows for normal operation: r14 = high, r15 = low, r16 = low. to dis- able ld output (i.e. set ld low), r14 should be set low. serial input data timing wave forms are shown in fig. 2. fig. 1 ? serial input data format fig. 2 ? serial input data timing waveforms control bit lsb msb 16-bit data for n-counter 13-bit data for r-counter r15 r16 r14 t su1 t su2 t hold data clk le data clk le msb 234567891011121314151617 1 lsb control bit
FS8107E page 8 april 2003 phase/frequency detector (pfd) the pfd compares an internal input frequency divider output signal, f v , with an internal reference frequency di vider output signal, f r , and generates an error signal, do, which is proportional to the phase error between f v and f r . the do output is inte nded for use with a passive filter as shown in fig. 3. the input/output waveforms for the pfd are shown in fig. 4. fig. 3 ? passive low-pass filter circuit fig. 4 ? pfd input/output waveforms do to vco r1 r2 c high-z high-z high-z f r f v do ld
FS8107E page 9 april 2003 quick-lock signal (db) the quick-lock output signal, db, is provided so that the pll may achieve higher speed locking. when connected, the db output eff ectively doubles the charge pump current out- put to the loop filter during the initial st art-up of the pll (when opr first goes high). once the pll phase error is within a specific tolerance, the quick-lock circuitry sets the db output to a high impedance state and the pll continues toward lock with its normal charge pump current. stand-by mode the stand-by mode for the pll is ente red by setting the opr pin low and v dd1 to 0 v while the circuit is in operation. in the stand-by mode, the xin and fin amplifiers, n - counter, and r -counter are stopped, the n - and r -counters are also reset, and the do and db outputs are set to the high impedance stat e. as long as voltage is supplied to v dd2 , data loaded to the latches is kept. to exit from stand-by mode to normal operation, the opr pin must be set high and volta ge must again be supplied to v dd1 .
FS8107E page 10 april 2003 application circuit test nc opr le data clk ld nc xin xout vdd2 db do vss fin vdd1 dc/dc converter cpu lcd driver lcd driver rom ram decoder lpf lna 1st mixer 1st if amplifier 2nd mixer 2nd if amplifier discriminator wave shaper frequency multiplier ( 2,3) 2nd lo 1st lo himark FS8107E
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